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RIGOR PRODUCT FAMILY
RigorFlow is a chip design full process management tool used to improve the efficiency and QoR of the entire project design. The concise and intuitive visual interface helps engineers improve work efficiency and engineering quality, and also helps managers quickly identify project progress and problem points. The design full process management also facilitates cross departmental collaboration and data extraction and summary display of designer's personal tasks. This tool supports customization and optimization, is compatible with secondary development in different scenarios, and helps standardize the entire process management of chip design. This tool has been implemented by well-known major clients.
RigorFlow Chip Design Flow management software
RigorCons timing constraint management software is an automated tool used to constrain and manage SDCs that run through multiple stages of digital chip backend design. The tool utilizes the constraint conditions that have been practiced for many years by RigorCons to automatically check and verify multiple SDCs in parallel, detect defects and errors in each SDC as early as possible, significantly reduce the time for manual review of SDCs, shorten the iteration cycle, avoid huge losses caused by chip out, and allow designers to have more energy to solve more difficult problems. This tool consists of five core engines: rule-based engine, formal based engine, equivalence engine, hierarchical engine, and timing budgeting engine. This tool has processed SDC files of over 4GB and has been validated in large clients.
RigorCons Static Timing Constraints signoff software
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RigorDRC Design Rule Check signoff software
RigorDRC is a comprehensive DRC (Design Rule Check) software that supports interconnect and unit/block design rule checks, advanced process node capabilities, and higher operating efficiency than similar foreign tools. It is more suitable for handling large-scale layouts and includes user-friendly graphical interface tools for designers to quickly repair and discover design violations.
RigorEMIR is a power reliability solution that uses modern computing architecture and is designed for ultra large scale digital circuits. It provides power, IR, EM, and other analysis with signoff accuracy. High performance solution with independent intellectual property rights, distributed computing architecture, multi physics model simulation, combined with RigorTime engine, covering power integrity analysis from RTL to gate level, full chip, and packaging, including static/dynamic EM/IR analysis, and providing users with a simple and friendly visual diagnostic interface to help designers detect potential design hazards early, quickly and efficiently, locating and providing repair solutions.
RigorEMIR Power and Signal Integrity Analysis software
RigorTime Static Timing Analysis software
RigorTime is a comprehensive static timing analysis and optimization tool designed to address state-of-the-art timing requirements, including signal integrity (SI) analysis, path based analysis (PBA), on-chip variation (LVF, OCV), multimode and multi angle analysis (MMMC), hierarchical analysis, and more. RigorTime is not just an analysis tool, it is also deeply integrated with the Rigor system. By using flexible scripting languages, the timing signoff is closely integrated with the design process, accelerating the time convergence speed of the entire design process and greatly improving the efficiency of design convergence.