Without the correct constraints, there is no correct analysis, and the correctness and integrity of the timing constraints are the prerequisites for the timing analysis to sign off. In recent years, soc chip systems have become more and more complex, bringing endless challenges to timing constraint management. TAI Constraints has a variety of functions such as constraint generation, management, and verification, making time-consuming and error-prone constraint signing simple and easy.
Static timing analysis is the gatekeeper of chip performance, which guides P&R, ECO and other tools to continuously improve and improve the timing performance of chips. TAI STA not only scrutinizes all timing paths in detail and analyzes latency with high accuracy, but also provides unique high-speed iteration solutions for large-scale, high-complexity chips such as GPUs, CPUs, 5Gs, and SOCs to accelerate the design process. TAI STA fully supports various STA functions, such as GBA, PBA, LVF, MMMC, etc
JetFlow is an software helps digital IC design flow management. It converts tens or hundreds of design steps into a visual flow, and helps designer to generate and manage EDA tasks. Our software is co-developed with expoerienced and large IC design team, which make it easy and transparent to manage complex design projects.
JetDRC is a physical verification tool that helps to examine whether GDS fits all foundry manufaction requirements. The IC design have billions of geometries in a GDS, which requires fast algorithms and distributed engine to check DRC rules efficiently. It divides a large layout into various zones, and utilize hundreds of CPUs for distributed checking.
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